LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY JKff_1 IS
PORT (J,K:IN STD_LOGIC;
clk : IN std_logic;
Q: out STD_LOGIC);
end JKff_1;
ARCHITECTURE behave OF JKff_1 IS
signal S:STD_LOGIC;
BEGIN
S<= (J and (not S)) or (S and (not K)) when clk'event and clk='0' ;
Q<=S ;
end behave;
上一篇:单片机红外解码查询法(HS9148)
下一篇:半加器的VHDL程序
推荐阅读最新更新时间:2024-03-16 14:04