OK6410裸机之DDR片外内存访问

start.S源码：

.globl _start

_start:

// 硬件相关的设置 

    // Peri port setup 

    ldr r0, =0x70000000

    orr r0, r0, #0x13

    mcr p15,0,r0,c15,c2,4       @ 256M(0x70000000-0x7fffffff)

// 关看门狗 

    // 往WTCON(0x7E004000)写0 

    ldr r0, =0x7E004000       // 伪指令 

    mov r1, #0

    str r1, [r0]

    bl clock_init

// 为调用C函数准备环境 

    ldr sp, =8*1024

    bl sdram_init

// 重定位代码 

    // 把片内内存中程序的代码段、数据段复制到它的链接地址去

    adr r0, _start         // 获得_start指令当前所在的地址 : 0

    ldr r1, =_start       // _start的链接地址 0x50000000 

    ldr r2, =bss_start  // bss段的起始链接地址 

    cmp r0,r1

    beq clean_bss

copy_loop:

    ldr r3, [r0], #4

    str r3, [r1], #4

    cmp r1, r2

    bne copy_loop    

// 把BSS段对应的内存清零 

clean_bss:

    ldr r0, =bss_start

    ldr r1, =bss_end

    mov r3, #0

    cmp r0, r1

    beq on_ddr

clean_loop:

    str r3, [r0], #4

    cmp r0, r1    

    bne clean_loop    

on_ddr:

    // 调用C函数 

    ldr pc, =main  // pc等于main的链接地址 

===================================================================

clock.S源码：

#define APLL_LOCK    0x7e00f000

#define MPLL_LOCK    0x7e00f004

#define EPLL_LOCK    0x7e00f008

#define LOCK_TIME    0xffff

#define OTHERS       0x7e00f900

#define CLK_DIV0     0x7e00f020

#define CLK_SRC      0x7e00f01c

.text

.global clock_init

clock_init:                //初始化系统时钟

    @ set the lock time to max

    ldr r0, =LOCK_TIME

    ldr r1, =APLL_LOCK

    str r0, [r1]

    ldr r1, =MPLL_LOCK

    str r0, [r1]

    ldr r1, =EPLL_LOCK

    str r0, [r1]    

    @ set async mode

    ldr r0, =OTHERS

    ldr r1, [r0]

    bic r1, #0xc0            

    str r1, [r0]

    loop1:

    ldr r0, =OTHERS

    ldr r1, [r0]

    and r1, #0xf00                    

    cmp r1, #0

    bne loop1        

    @ set the divider

    #define DIV_VAL    ( (0)|(1<<4)|(1<<8)|(1<<9)|(3<<12) )

    ldr r0, =CLK_DIV0

    ldr r1, =DIV_VAL

    str r1, [r0]    

    @ set APLL, MPLL, EPLL        

    #define SDIV    1

    #define PDIV    3

    #define MDIV    266    

    #define PLL_ENABLE    ( 1 << 31 )

    #define APLL_VAL    ( (SDIV<<0)|(PDIV<<8)|(MDIV<<16)|(PLL_ENABLE) )

    #define MPLL_VAL    APLL_VAL

    #define EPLL0_VAL    ( (2<<0)|(1<<8)|(32<<16)|PLL_ENABLE)

    #define EPLL1_VAL    ( 0 )

    #define APLL_CON    0x7e00f00c

    #define MPLL_CON    0x7e00f010

    #define EPLL_CON0    0x7e00f014

    #define EPLL_CON1    0x7e00f018

    ldr r0, =APLL_CON

    ldr r1, =APLL_VAL

    str r1, [r0]

    ldr r0, =MPLL_CON

    ldr r1, =MPLL_VAL

    str r1, [r0]

    ldr r0, =EPLL_CON0

    ldr r1, =EPLL0_VAL

    str r1, [r0]

    ldr r0, =EPLL_CON1

    ldr r1, =EPLL1_VAL

    str r1, [r0]

    @ select the source                     

    ldr r0, =CLK_SRC

    mov r1, #7

    str r1, [r0]

    mov pc, lr                

====================================================================

sdram.c源码：

#include "common.h"

#define MEMCCMD         0x7e001004

#define P1REFRESH         0x7e001010

#define P1CASLAT           0x7e001014

#define MEM_SYS_CFG    0x7e00f120

#define P1MEMCFG         0x7e00100c

#define P1T_DQSS            0x7e001018

#define P1T_MRD             0x7e00101c

#define P1T_RAS              0x7e001020

#define P1T_RC                0x7e001024

#define P1T_RCD              0x7e001028

#define P1T_RFC               0x7e00102c

#define P1T_RP                 0x7e001030

#define P1T_RRD              0x7e001034

#define P1T_WR               0x7e001038

#define P1T_WTR             0x7e00103c

#define P1T_XP                0x7e001040

#define P1T_XSR              0x7e001044

#define P1T_ESR              0x7e001048

#define P1MEMCFG2      0X7e00104c

#define P1_chip_0_cfg     0x7e001200

#define P1MEMSTAT       0x7e001000

#define P1MEMCCMD     0x7e001004

#define P1DIRECTCMD    0x7e001008

#define HCLK    133000000

#define nstoclk(ns)    (ns/( 1000000000/HCLK)+1)

//初始化DDR

int sdram_init( void )

{

    // tell dramc to configure                

    set_val( MEMCCMD, 0x4 );

    // set refresh period    

    set_val( P1REFRESH, nstoclk(7800) );

    // set timing para        

    set_val( P1CASLAT, ( 3 << 1 ) );  

    set_val( P1T_DQSS, 0x1 );    // 0.75 - 1.25

    set_val( P1T_MRD, 0x2 );

    set_val( P1T_RAS, nstoclk(45) );

    set_val( P1T_RC, nstoclk(68) );        

    u32 trcd = nstoclk( 23 );

    set_val( P1T_RCD, trcd | (( trcd - 3 ) << 3 ) );

    u32 trfc = nstoclk( 80 );

    set_val( P1T_RFC, trfc | ( ( trfc-3 ) << 5 ) );   

    u32 trp = nstoclk( 23 );

    set_val( P1T_RP, trp | ( ( trp - 3 ) << 3 ) ); 

    set_val( P1T_RRD, nstoclk(15) );

    set_val( P1T_WR, nstoclk(15) );

    set_val( P1T_WTR, 0x7 );

    set_val( P1T_XP, 0x2 );

    set_val( P1T_XSR, nstoclk(120) );

    set_val( P1T_ESR, nstoclk(120) );

    // set mem cfg 

    set_nbit( P1MEMCFG, 0, 3, 0x2 );     // 10 column address 

    // set_nbit: 把从第bit位开始的一共len位消零，然后把这几位设为val 

    //set_nbit( P1MEMCFG, 3, 3, 0x2 );  // 13 row address 

    set_nbit( P1MEMCFG, 3, 3, 0x3 );     // 14 row address 

    set_zero( P1MEMCFG, 6 );                // A10/AP 

    set_nbit( P1MEMCFG, 15, 3, 0x2 );   // Burst 4 

    set_nbit( P1MEMCFG2, 0, 4, 0x5 );

    set_2bit( P1MEMCFG2, 6, 0x1 );       // 32 bit 

    set_nbit( P1MEMCFG2, 8, 3, 0x3 );   // Mobile DDR SDRAM 

    set_2bit( P1MEMCFG2, 11, 0x1 );

    set_one( P1_chip_0_cfg, 16 );           // Bank-Row-Column organization 

    // memory init

    set_val( P1DIRECTCMD, 0xc0000 );  // NOP

    set_val( P1DIRECTCMD, 0x000 );      // precharge

    set_val( P1DIRECTCMD, 0x40000 );  // auto refresh

    set_val( P1DIRECTCMD, 0x40000 );  // auto refresh

    set_val( P1DIRECTCMD, 0xa0000 );  // EMRS

    set_val( P1DIRECTCMD, 0x80032 );  // MRS

    set_val( MEM_SYS_CFG, 0x0 );

    // set dramc to "go" status    

    set_val( P1MEMCCMD, 0x000 );

    // wait ready

    while( !(( read_val( P1MEMSTAT ) & 0x3 ) == 0x1));

}

==================================================================

led.c源码：

void delay(volatile int count)

{

    volatile int i = count;

    while(i)

    {

        i--;

    }

}

//int i = 0xf;                                     // 位于数据段 

int i = 0;                                           // 位于BSS段 

volatile const int j = 0x12345678;  // 位于只读数据段 

//volatile int k=0;                            // bss段 

int main()

{

    // 配置GPMCON让GPM0,1,2,3作为输出引脚 

    volatile unsigned long *gpmcon = (volatile unsigned long *)0x7F008820;

    volatile unsigned long *gpmdat = (volatile unsigned long *)0x7F008824;

    *gpmcon &= ~(0xffff);

    *gpmcon |= 0x1111;

    // 循环点亮这4个LED 

    while (1)

    {

        *gpmdat &= ~0xf;

        *gpmdat |= i;

        i++;

        delay(20000);

        if (i == 16)

            i = 0;

    }

    return 0;

}

====================================================================

Makefile文件：

led.bin : start.o clock.o sdram.o led.o

    arm-linux-ld  -T led.lds -o led.elf $^

    arm-linux-objcopy -O binary led.elf led.bin

    arm-linux-objdump -D led.elf > led.dis

%.o : %.S

    arm-linux-gcc -g -c -O2 -o $@ $^

%.o : %.c

    arm-linux-gcc -g -c -O2 -o $@ $^

clean:

    rm -f *.o *.bin *.elf *.dis    

====================================================================

led.lds文件：

SECTIONS 

{

    . = 0x50000000;

    .text : 

    { 

        start.o 

        * (.text)

    } 

    . = ALIGN(4);

    .rodata :

    {

        * (.rodata)

    }

    . = ALIGN(4);

    .data :

    {

        * (.data)

    }

    . = ALIGN(4);    

    bss_start = . ;  // 0x50000450 

    .bss :

    {

        * (.bss)        // i 

        * (.common)

    }

    bss_end = . ;    // 0x50000450 

}

===================================================================

引脚定义：Xm1RAS ：Row address strobe (active low)，行地址锁存信号

                 Xm1CAS ： Column address strobe (active low)，列地址锁存信号

                 Xm1WEN：Write enable (active low) ，写使能