STM32F107VC 锁相环初始化

AHB：advanced high-performance bus；APB： advanced peripherals bus。

static void SetSysClockTo72(void)
{
  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  
  /*

     SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------

      SYSCLK   由PLL时钟，外部高速时钟，内部高速时钟获得，最大为72MHz

      HCLK       由HCLK经过AHB预分频器得到，最大72MHz，至AHB总线，核心存储器和DMA

      PCLK2     最大72MHz ,至APB2 外设

      PCLK1     最大36MHz，至APB1外设

*/    
  /* 使能高速外部晶振*/    
  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
 
  /* 等待外部高速时钟稳定*/
  do
  {
    HSEStatus = RCC->CR & RCC_CR_HSERDY;
    StartUpCounter++;  
  } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));

  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
  {
    HSEStatus = (uint32_t)0x01;
  }
  else
  {
    HSEStatus = (uint32_t)0x00;
  } 

  if (HSEStatus == (uint32_t)0x01)
  {
    /* FLASH 存取控制寄存器配置  使能预取，两个等待周期（36MHz --72MHz为2个等待周期）*/
    FLASH->ACR |= FLASH_ACR_PRFTBE;

    /* Flash 2 wait state */
    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;   

    /* 先对HCLK PCLK1 PCLK2初始化

       时钟配置寄存器   上电初始化初值应为为 0 如下配置的结果是：

       8M的高速内部时钟为系统时钟

       HCLK = 8M

       PCLK2 = 8M

       PCLK1 = 4M

 */
    /* HCLK = SYSCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
      
    /* PCLK2 = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
    
    /* PCLK1 = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;

#ifdef STM32F10X_CL
    /* Configure PLLs ------------------------------------------------------*/

    /* 如果定义了STM32F10x_CL 则进行如下 配置 该宏定义在编译选项中定义 */
    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
    /*

        PLL2 配置： 时钟信号输入源为PREDIV1, 8倍频后5分频 
   */

    /*清零相关控制域*/      

  RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);

   /* 配置CFGR2寄存器*/
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
  
    /* Enable PLL2 */
    RCC->CR |= RCC_CR_PLL2ON;
    /* Wait till PLL2 is ready */
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
    {
    }
    
   
    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
                            RCC_CFGR_PLLMULL9); 
#else    
    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
                                        RCC_CFGR_PLLMULL));
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
#endif /* STM32F10X_CL */

   /* Enable PLL   使能PLL */
    RCC->CR |= RCC_CR_PLLON;

    /* Wait till PLL is ready */
    while((RCC->CR & RCC_CR_PLLRDY) == 0)
    {
    }
    
    /*

      Select PLL as system clock source

       选择PLL时钟作为系统时钟，并等待稳定 

 */ 
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;   

    /* Wait till PLL is used as system clock source */
    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
    {
    }
  }
  else
  { /* If HSE fails to start-up, the application will have wrong clock 
         configuration. User can add here some code to deal with this error */
  }
}

HSE(25MHZ)->PREDIV2(5分频)——5MHZ——>PLL2MUL(8倍频)——40MHZ——>PREDIV1SCR(选择PLL2)——40MHZ——>PREDIV1(5分频)——8MHZ——>PLLSCR(PREDIV1输入)——8MHZ——>PLLMUL(9倍频)——72MHZ——>SW(选择PLL)——SYSCLK(72MHZ).