Micro2440 Nboot ADS 移植到Keil5编译通过

由于项目需要开发老版本S3C2440，由于时间有限系统当然跑WinCE6.0，软件兼容性好 当然安装开发工具等等一大堆是相当头疼，之前做STM32特别多，个人电脑一大堆都是32的BSP包，keil用的特别顺手，这次开发2440需要用到友善提供的Nboot，由于ADS软件兼容行特差问题太多不想折腾了，将Nboot移植到keil5上，

步骤1：

需要下载keil下ARM9的支持包，给上逻辑 http://www2.keil.com/mdk5/legacy，下载Legacy support for Arm7, Arm9 & Cortex-R devices安装即可。

步骤2：

将所有Nboot文件拷贝到keil工程下，如下：

步骤3：keil配置

这里需要自己编写链接文件

如下配置：

LOAD_ROM 0x0 ABSOLUTE 

{

INIT 0x0 ABSOLUTE 0x0fff    ;初始程序放在STONE RAM内，起始地址为0，地址尺寸限制为0XFFF（4kb）

{              ;|Image$$INIT$$Base|

*.o(Init,First);|Image$$INIT$$Limit|

}

RO+0 ABSOLUTE   ;主程序放在SDRAM内，起始地址为|Image$$INIT$$Limit|+0x30000000

{           ;|Image$$ALL_RO$$Base|

*.o(+RO)   ;|Image$$ALL_RO$$Limit|

}

RW+0x0

{

.ANY (+RW)

}

ZI+0x0

{

.ANY (+ZI)

}

}

步骤4：

修改244x_init.s文件，有的定义跟keil汇编不太一样

;=========================================

; NAME: 2442INIT.S

; DESC: C start up codes

;       Configure memory, ISR ,stacks

; Initialize C-variables

; HISTORY:

; 2002.02.25:kwtark: ver 0.0

; 2002.03.20:purnnamu: Add some functions for testing STOP,Sleep mode

; 2003.03.14:DonGo: Modified for 2440.

;=========================================

;  IMPORT  __use_no_semihosting_swi

GET memcfg.inc

GET 244X_addr.inc

;_STACK_BASEADDRESS EQU 0x34000000

;SVCStack EQU _STACK_BASEADDRESS ;0x33ff5800 ~

;---------------------------------------------------------------------------

;处理器模式 

USERMODE EQU  0x10 

FIQMODE EQU  0x11 

IRQMODE EQU  0x12 

SVCMODE EQU  0x13 

ABORTMODE EQU  0x17 

UNDEFMODE EQU  0x1b 

SYSMODE EQU 0x1f 

;相关掩码 

MODEMASK     EQU  0x1f 

NOINT EQU  0xc0 

;各个处理器模式下堆栈设置 

_STACK_BASEADDRESS EQU 0x33ff8000 

;BANK6 64MB顶部 

UserStack EQU (_STACK_BASEADDRESS-0x3800) ;0x33ff4800 ~ 

SVCStack EQU (_STACK_BASEADDRESS-0x2800) ;0x33ff5800 ~ 

UndefStack EQU (_STACK_BASEADDRESS-0x2400) ;0x33ff5c00 ~ 

AbortStack EQU (_STACK_BASEADDRESS-0x2000) ;0x33ff6000 ~ 

IRQStack EQU (_STACK_BASEADDRESS-0x1000) ;0x33ff7000 ~ 

FIQStack EQU (_STACK_BASEADDRESS-0x0) ;0x33ff8000 ~ 

IMPORT  |Image$$RO$$Limit|  ; End of ROM code (=start of ROM data) 

IMPORT  |Image$$RW$$Base|   ; Base of RAM to initialise 

IMPORT  |Image$$ZI$$Base|   ; Base and limit of area 

IMPORT  |Image$$ZI$$Limit|  ; to zero initialise 

IMPORT  Main    ; The main entry of mon program

PRESERVE8    ;8 字对齐(为了让汇编代码8字节对齐)

AREA    Init,CODE,READONLY;AREA    Init,CODE,READONLY修改

ENTRY

b ResetHandler

b . ;handler for Undefined mode

b . ;handler for SWI interrupt

b . ;handler for PAbort

b . ;handler for DAbort

b . ;reserved

b . ;handler for IRQ interrupt

b . ;handler for FIQ interrupt

;======================================================================================

; ENTRY

;======================================================================================

ResetHandler

; 向寄存器地址写入 0即关闭看门狗

ldr r0,=WTCON       ;watch dog disable  0x53000000       ;Watch-dog timer mode

ldr r1,=0x0

str r1,[r0]

ldr r0,=INTMSK ;0x4a000008    ;Interrupt mask control

ldr r1,=0xffffffff  ;all interrupt disable

str r1,[r0] ;/向该地址写入全1 屏蔽所有中断

ldr r0,=INTSUBMSK

ldr r1,=0x7ff ;all sub interrupt disable

str r1,[r0]

ldr r0,=GPBCON ;//设置IO PG

ldr r1,=(1<<10):or:(1<<12):or:(1<<14):or:(1<<16); set output

str r1,[r0] ;//写入PG寄存器

ldr r0,=GPBDAT ;set high.

ldr r1,=(1<<6):or:(1<<7):or:(1<<8) ;//点亮LED1  

str r1,[r0]

;To reduce PLL lock time, adjust the LOCKTIME register.

ldr r0,=LOCKTIME

ldr r1,=0xffffff

str r1,[r0]

;设置时钟分频

ldr r0,=CLKDIVN

ldr r1,=5

str r1,[r0]

;Configure UPLL

ldr r0,=UPLLCON

ldr r1,=((56<<12)+(2<<4)+2)  ;Fin=12MHz,Fout=48MHz

str r1,[r0]

nop ; Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.

nop

nop

nop

nop

nop

nop

;Configure MPLL

ldr r0,=MPLLCON

;ldr r1,=((92<<12)+(1<<4)+1)

ldr r1,=((125<<12)+(1<<4)+1);12.0000MHz 532.00 MHz 125(0x7d) 1 1

str r1,[r0]

; :::::::::::::::::::::::::::::::::::::::::::::

;           BEGIN: Power Management 

; - - - - - - - - - - - - - - - - - - - - - - -

ldr r1,=GSTATUS2

ldr r0,[r1]

tst r0,#0x2

beq %F4

ldr r1, =MISCCR        ; MISCCR's Bit 17, 18, 19 -> 0

ldr r0, [r1]                ; I don't know why, Just fallow Sample Code.

bic r0, r0, #(3 << 17)      ; SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:L->H

str r0, [r1]

; Set memory control registers

add r0, pc, #SMRDATA - (. + 8)

ldr r1, =BWSCON ; BWSCON Address

add r2, r0, #52 ; End address of SMRDATA

loop10

ldr r3, [r0], #4

str r3, [r1], #4

cmp r2, r0

bne loop10

mov r1, #256

loop11

subs r1, r1, #1 ; wait until the SelfRefresh is released.

bne loop11

ldr r0,=GPBDAT ;set high.

ldr r1,=(1<<7):or:(1<<8) ;//点亮LED2  

str r1,[r0]

; ldr r1,=GSTATUS3 ;GSTATUS3 has the start address just after SLEEP wake-up

;  如何保证跳过去的前提是内存数据正确!

ldr r2, =0x201000 ; offset into the RAM 

add r2, r2, #0x30000000 ; add physical base

mov     pc, r2 ;  & jump to StartUp address

nop

nop

nop

b .

; - - - - - - - - - - - - - - - - - - - - - - -

;           END: Power Management 

; :::::::::::::::::::::::::::::::::::::::::::::

4

    ; Configure memory controller

    ;ldr    r0,=SMRDATA

    add     r0, pc, #SMRDATA - (. + 8)

ldr r1,=BWSCON ;BWSCON Address

add r2, r0, #52 ;End address of SMRDATA

0

ldr r3, [r0], #4

str r3, [r1], #4

cmp r2, r0

bne %B0

    ;Initialize stacks

bl InitStacks

;ldr sp,=SVCStack ; 

;Copy and paste RW data/zero initialized data

LDR     r0, =|Image$$RO$$Limit| ; 装入RO段结束地址 

LDR     r1, =|Image$$RW$$Base|  ; 装入RW段起始地址 

LDR     r3, =|Image$$ZI$$Base|  ; 装入ZI段起始地址 

;Zero init base => top of initialised data

cmp r0, r1      ; Check that they are different

beq %F2

1

cmp r1, r3      ; Copy init data

ldrcc r2, [r0], #4    ;--> LDRCC r2, [r0] + ADD r0, r0, #4

strcc r2, [r1], #4    ;--> STRCC r2, [r1] + ADD r1, r1, #4

bcc %B1

2

LDR     r1, =|Image$$ZI$$Limit|  

mov r2, #0

3

cmp r3, r1      ; Zero init

strcc r2, [r3], #4

bcc %B3

ldr r0,=GPBDAT ;set high.

ldr r1,=(1<<6):or:(1<<8) ;//点亮LED3  

str r1,[r0]

; MMU_EnableICache

mrc p15,0,r0,c1,c0,0

orr r0,r0,#(1<<12)

mcr p15,0,r0,c1,c0,0

; MMU_EnableDCache

mrc p15,0,r0,c1,c0,0

orr r0,r0,#(1<<2)

mcr p15,0,r0,c1,c0,0

bl Main ;Don't use main() because ......

b .

;function initializing stacks

InitStacks

;Don't use DRAM,such as stmfd,ldmfd......

;SVCstack is initialized before

;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'

mrs r0,cpsr

bic r0,r0,#MODEMASK

orr r1,r0,#UNDEFMODE:or:NOINT

msr cpsr_cxsf,r1 ;UndefMode

ldr sp,=UndefStack ; UndefStack=0x33FF_5C00

orr r1,r0,#ABORTMODE:or:NOINT

msr cpsr_cxsf,r1 ;AbortMode

ldr sp,=AbortStack ; AbortStack=0x33FF_6000

orr r1,r0,#IRQMODE:or:NOINT

msr cpsr_cxsf,r1 ;IRQMode

ldr sp,=IRQStack ; IRQStack=0x33FF_7000

orr r1,r0,#FIQMODE:or:NOINT

msr cpsr_cxsf,r1 ;FIQMode

ldr sp,=FIQStack ; FIQStack=0x33FF_8000

bic r0,r0,#MODEMASK:or:NOINT

orr r1,r0,#SVCMODE

msr cpsr_cxsf,r1 ;SVCMode

ldr sp,=SVCStack ; SVCStack=0x33FF_5800

;USER mode has not be initialized.

mov pc,lr

;The LR register won't be valid if the current mode is not SVC mode.

LTORG

SMRDATA DATA

; Memory configuration should be optimized for best performance

; The following parameter is not optimized.

; Memory access cycle parameter strategy

; 1) The memory settings is  safe parameters even at HCLK=75Mhz.

; 2) SDRAM refresh period is for HCLK<=75Mhz.

DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))

DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))   ;GCS0

DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))   ;GCS1

DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))   ;GCS2

DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))   ;GCS3

DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))   ;GCS4

DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))   ;GCS5

DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))    ;GCS6

DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))    ;GCS7

DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Tsrc<<18)+(Tchr<<16)+REFCNT)

;;;

;   DCD 0x00aC03F4 ;refresh

DCD 0xB2     ;SCLK power saving mode, BANKSIZE 128M/128M

DCD 0x30     ;MRSR6 CL=3clk

DCD 0x30     ;MRSR7 CL=3clk

ALIGN

; AREA RamData, DATA, READWRITE

; ^   _ISR_STARTADDRESS ; MAP  _ISR_STARTADDRESS=0x33FF_FF00

;vCLKDIV_VAL DCD CLKDIV_VAL

;vMPLL_VAL DCD ((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV)