挑战摩尔定律

      过去的几个月中，我和一些同事试图努力阐明IC架构的未来。至少有一点是肯定的：我们不希望生活在摩尔定律总是在发挥作用的世界。在这里，我要讲讲为什么我这么想，也希望听听你们的观点。

      按照现在的处理器架构发展下去，我们很可能就会迷失自己的方向。第一台微型处理器的应用使我们可以实时完成对一些简单的信号的处理。这时候，阵列处理器和微型计算机被认为是用作信号处理的先进工具，是研究机构的首选。正当研究人员研究和发展新的信号处理概念和算法时，另一群技术专家开始着手研究第一个DSP芯片。大约20年前，在晶体管发明之后，第一个商业应用DSP出现在市场上，并且很快的改变了我们的世界。

      DSP的早期应用主要是在减少乘法运算方面，因为在硬件中运用乘法速度缓慢代价昂贵。DSP的重大突破是把一种特殊的乘法硬件加入到微处理器之中。这项发明改变了DSP的主要应用方向：使之从减少乘法运算数量到最佳化的进行乘法加法运算。

      另一方面原因导致了DSP架构的快速发展：就是哈佛架构（有两条总线：一条是程序存储一条是数据存储）而不是诺依曼架构（只有一条总线：程序和数据共享同一存储空间）。为了更好的适应大数据量计算处理器的需求，哈佛的两条总线架构可在修改后支持程序和数据，使两条总线都可以满足运算。

      为了利用高速计算的能力，研发出新的指令使必要的操作在一个指令周期下完成计算。后来，添加了重复操作并成了我们熟悉的MAC功能。

      DSP架构进一步的被更新。结合哈佛和诺依曼架构的优点形成了多总线路诺依曼架构。当IC应用增加时， VLIW超常指令字(Very Long Instruction Word)的概念被引入, 用于并行处理中以满足实时限制功能。

      现代架构继续对性能和效率的限制施加压力，通过创新，如加深管线，扩大分支预测技术和先进的指令集。这些创新，反过来又创造了新的挑战，尽管他们克服以往的一些限制，我计划在未来的专栏中继续讨论这个问题。

附：方进专栏原文

The Challenge with Moore’s law

Over the last several months, I’ve been working with some of my colleagues to articulate the future of IC architectures. One of the things that is clear, we are no longer in a world where Moore’s law can and should always apply. Here I’m trying to outline why I think that is and look forward to hearing what your thoughts are on the topic.

When following the progression of modern processor architectures, it is possible to see where we may have lost our way. The introduction of the first microprocessor allowed us to process very simple signals in real time. During this time, the array processor and mini-computer were considered the state-of-the-art tools for signal processing and premier choice in the research community. As researchers discovered and developed new signal processing concepts and algorithms, another community of technologists were already on the path to creating the first DSP device. Approximately 20 years after the invention of the transistor, the first commercially available DSPs appeared on the market and dramatically changed the future of the world.

Early work in DSP algorithm implementation focused on reducing the number of multiplications since multiplies were expansive and slow when implemented in hardware. The primary breakthrough of widespread DSP adoption was the addition of a specialized hardware multiplier to the microprocessor. This innovation changed the focus of digital signal processing from reducing the number of multiplies required by an algorithm to instead, optimizing the numbers of necessary multiplies and additions. 

Another major facet of the fast evolving DSP architecture was the use Harvard architecture (two busses – one for program memory and one for data memory) rather than Von Neuman architecture (a single bus with program and data sharing the same memory space). To better suit the needs of mathematically intense processors, the two busses of the Harvard architecture were modified to support both program and data memory allowing both busses to feed the multiplier.

To take advantage of the accelerated multiplication capabilities, new instructions were created to bring together the necessary operations to perform a multiply in a single instruction cycle. Later, the accumulate operation was added to create the familiar MAC function.

Further improvements to the DSP architecture followed. Combining the best of both the Harvard and Von Neuman architectures resulted in a multiple bus Von Neuman-style architecture. As IC performance increased, the concept of the Very Long Instruction Word (VLIW) was introduced allowing parallel processing to meet real-time constraints.

Modern architectures continue to press the limits of performance and efficiency through innovations such as deep pipelines, extensive branch prediction technology and advanced instruction sets. These innovations, in turn create new challenges even as they overcome previous limitations, which I plan to discuss in several future blogs.