tp

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课时1：英飞凌 - 保护嵌入式设备与系统的完整性和可靠性 课时2：大联大 - 可信计算模组TPM在服务器产品的应用

本视频演示 TPS65218D0 PMIC 的用户编程功能。 TPS65218D0 现在提供非易失性存储器的自定义编程，允许快速原型设计和轻松定制。...

课时1：TPS65218D0：多轨电源管理IC（PMIC）的用户编程

This video will demonstrate the user programming feature of the PMIC TPS65086100....

课时1：TPS65086100：多轨电源管理IC的用户编程

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课时1：使用TI Fusion Digital Power Designer软件工具和TPSM846C23 PMBus电源模块进行设计

LDO输出噪声来自哪里？...

课时1：LDO Output Noise

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课时1：TPS61178 20-V、10-A全集成升压变换器

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课时1：升压变换器TPS61088的输出短路保护方案

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课时1：TPS56x201/8 直流降压器简介

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课时1：支持多种工作模式，输出5V/开关电流为4A的升压变换器 TPS61253A

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课时1：TI 提供的闭环低物料清单 (BOM) 放大器解决方案(TPA3140 和 TAS5720)

LTpowerCAD 设计工具专门针对采用凌力尔特的 μModule 和单片式 DC/DC 稳压器产品之用户应用提供推荐的组件值和性能估计值。...

课时1：LTpowerCAD II： 开关稳压电源设计工具

LTC2978 具有使能电源监控、监视、排序和修整功能、以及无可比拟的准确度。这些特点与我们的易用型 GUI 相组合，可帮助电源设计人员以过去所需的部份时间来完成复杂电源管理方案的定义和实现工作。故障记录能力实现电源故障的系统级调试。...

课时1：采用 LTpowerPlay 来管理 LTC2978

基于Zynq-7000平台运行SoftPLC的解决方案，集成了KW-SoftPLC，PowerLink实时以太网协议，Linux操作系统，用以快速、精准的实现工业控制应用...

课时1：在Zynq平台运行SoftPLC方案

Lecture slides can be found on the EnICS Labs web site at:  https://enicslabs.com/academic-courses/dvd-english...

课时1：1a Introduction 课时2：1b Building a Chip 课时3：1c Design Automation 课时4：1d The Chip Design Flow 课时5：Introduction 课时6：2a_ Verilog 课时7：2b_ Verilog Syntax 课时8：2c_ Simple Verilog Examples 课时9：2d_ Verilog FSM Implementation 课时10：2e- Coding Style for RTL - part 1 课时11：How to write Synthesizeable RTL 课时12：Verilog HDL 课时13：3a_ Logic Synthesis - Part 1 课时14：3b_ HDL Compilation 课时15：3c- Library Definition 课时16：3d- LEF 课时17：3e_ Liberty (.lib) 课时18：3f- Contents of Standard Cell Libraries 课时19：Logic Synthesis Part 1 课时20：4a_ Logic Synthesis - Part 2 课时21：4b_ BDDs and Boolean Minimization 课时22：4c_ Constraint Definition 课时23：4d_ Technology Mapping 课时24：4e_ Verilog for Synthesis - revisited 课时25：4f- Timing Optimization 课时26：Logic Synthesis Part 2 课时27：5a_ Timing Analysis 课时28：5b_ Timing Constraints 课时29：5c_ Static Timing Analysis (STA) 课时30：5d_ STA Example 课时31：5e_ Design Constraints (SDC) 课时32：5f_ SDC Continued. 课时33：5g_ Timing Reports 课时34：5h_ Multi-Mode Multi-Corner (MMMC) 课时35：Timing Analysis 课时36：6a_ Moving to the Physical Domain 课时37：6b- Multiple Voltage Domains 课时38：6c_ Floorplanning 课时39：6d_ Hierarchical Design 课时40：6e- Power Planning 课时41：Moving to the Physical Domain 课时42：7a_ Standard Cell Placement 课时43：7b_ Random Placement 课时44：7c_ Analytic Placement 课时45：7d- Analytic Placement Example 课时46：7e_ Placement in Practice 课时47：Placement 课时48：8a_ Clock Tree Synthesis (CTS) 课时49：8b_ Clock Distribution 课时50：8c_ Clock Concurrent Optimization (CCOpt) 课时51：8d- Clock Tree Synthesis in EDA Tools 课时52：8e_ Clock Routing and Clock Tree Analysis 课时53：8f_ Clock Generation 课时54：8g_ Clock Domain Crossing (CDC) 课时55：CTS 课时56：9a- Routing 课时57：9b_ Maze Routing 课时58：9c_ Maze Routing (continued) 课时59：9d- Routing in Practice 课时60：9e- Signal Integrity (SI) and Design for Manufacturing (DFM) 课时61：Routing 课时62：10a- Packaging 课时63：10b- I_O Circuits - Digital IOs 课时64：10c- I_O Circuits - Analog IOs, ESD Protection, Pad Configurations 课时65：10d- System-in-Package (SiP) 课时66：I_O and Packaging 课时67：11a_ Sign-off Timing 课时68：11b- Additional issues in Sign-off Timing 课时69：11c_ Chip Finishing, including Density Fill and Antenna Fixes 课时70： 11d- Sign-off Validation, including IR Drop and EM Analysis, LEC, and DRC_LVS_ERC 课时71：Chip Finishing and Signoff 课时72：Introduction to Tcl-The tool command language-Part1 课时73：Introduction to Tcl-The tool command language-Part2

台湾省清华大学工程与系统科学系研究所与大三大四半导体制程与整合专业课程 2021版  https://ycwuess.wixsite.com/semiconductorlab ...

课时1：Ep0 Semiconductor Engineering 课时2：[预告片] Ep1 Semiconductor Engineering 课时3：Ep1 Semiconductor Engineering 课时4：Ep2 Semiconductor Engineering 课时5：Ep3 Semiconductor Engineering 课时6：Ep4 Semiconductor Engineering 课时7：Ep5 Semiconductor Engineering 课时8：Ep6 Semiconductor Engineering 课时9：Ep7 Semiconductor Engineering 课时10：Ep8 Semiconductor Engineering 课时11：Ep9 Semiconductor Engineering 课时12：Ep10 Semiconductor Engineering 课时13：Ep11 Semiconductor Engineering 课时14：Ep12 Semiconductor Engineering 课时15：Ep13 Semiconductor Engineering 课时16：Ep14 Semiconductor Engineering 课时17：Ep15 Semiconductor Engineering 课时18：Ep16 Semiconductor Engineering 课时19：Ep17 Semiconductor Engineering 课时20：Ep18 Semiconductor Engineering 课时21：Ep19 Semiconductor Engineering 课时22：Ep20 Semiconductor Engineering 课时23：Ep21 Semiconductor Engineering 课时24：Ep22 Semiconductor Engineering 课时25：Ep23 Semiconductor Engineering 课时26：Ep24 Semiconductor Engineering 课时27：Ep25 Semiconductor Engineering 课时28：Ep26 Semiconductor Engineering 课时29：Ep27 Semiconductor Engineering 课时30：Ep28 Semiconductor Engineering 课时31：Ep29 Semiconductor Engineering 课时32：Ep30 Semiconductor Engineering 课时33：Ep31 Semiconductor Engineering 课时34：Ep32 Semiconductor Engineering 课时35：Ep33 Semiconductor Engineering 课时36：Ep34 Semiconductor Engineering 课时37：Ep35 Semiconductor Engineering 课时38：Ep36 Semiconductor Engineering

See https://tinymlbook.com for more information....

课时1：TinyML Book Introduction 课时2：TinyML Book Screencast #1 - Training the Hello World model 课时3：TinyML Book Screencast #2 - Deploying the Hello World model on an Arduino 课时4：TinyML Book Screencast #3 - Introduction to TensorFlow Lite for Microcontrollers 课时5：TinyML Book Screencast #4 - Quantization 课时6：The Fall of Wirecard- A story of seers, deceivers and the deceived - Documentary - DokThema - BR

更多详情请访问： http://bbs.eeworld.com.cn/thread-1221433-1-1.html B站链接： 【报靶器】 https://www.bilibili.com...

课时1：报靶器

了解更多北京大学区块链课程的信息， 获取课程相关资料请访问肖臻老师的homepage：http://zhenxiao.com/,肖臻老师的微信：Excellent_Health。...

课时1：课程介绍 课时2：BTC 密码学原理 课时3：BTC 数据结构 课时4：BTC 协议 课时5：BTC 实现 课时6：BTC 网络 课时7：BTC 挖矿难度 课时8：BTC 挖矿 课时9：BTC 比特币脚本 课时10：BTC 分叉 课时11：BTC 问答 课时12：BTC 匿名性 课时13：BTC 思考 课时14：ETH 以太坊概述 课时15：ETH-账户 课时16：ETH 状态树 课时17：ETH 交易树和收据树 课时18：ETH GHOST 课时19：ETH 挖矿算法 课时20：ETH 难度调整 课时21：权益证明 课时22：ETH 智能合约 课时23：ETH TheDAO 课时24：ETH 反思 课时25：ETH 美链 课时26：总结 课时27：《科技向未来·区块链 “链”接未来》下篇 课时28：隐私计算 云栖大会 课时29：肖老师讲元宇宙

STM32Cube ecosystem and Azure RTOS libraries Materials related to this session you can find at: https...

课时1：Introduction and agenda 课时2：AzureRTOS and STM32Cube 课时3：ThreadX lab overview 课时4：ThreadX lab - step0 - LED blinky, no OS 课时5：ThreadX lab - step1 - First thread creation 课时6：ThreadX lab - step2 - TraceX activation 课时7：ThreadX lab - step3 - Concurent threads 课时8：ThreadX lab - step4 - CMSIS_OS2 wrapper 课时9：ThreadX lab - step5 - ThreadX features 课时10：ThreadX lab - step6 - Other ThreadX component 课时11：FileX overview 课时12：FileX integration into STM32Cube 课时13：FileX lab 课时14：USBX overview 课时15：USBX lab - composite device 课时16：NetX introduction 课时17：NetX overview 课时18：NetX web server demo 课时19：NetX examples overview 课时20：Conclusion

Lecture notes available on course website  http://cc.ee.ntu.edu.tw/~cmli/VLSItes......

课时1：Introduction What Is Testing 课时2：Introduction Types Of Tests 课时3：Introduction TestQuality 课时4：Introduction Test Economics 课时5：ReferenceDedication (_optional) 课时6：LogicSim Intro 课时7：LogicSim Model 课时8：LogicSim CompliedCode 课时9：LogicSim EventDriven 课时10：LogicSim Parallel 课时11：LogicSim Issues (_ optional) 课时12：FaultModeling Intro 课时13：FaultModeling SSF 课时14：FaultModeling BridgeFault 课时15：FaultModeling DelayFault 课时16：FaultModeling TransistorFault (_ optional) 课时17：FaultModeling_ FaultDetect,FaultCoverage 课时18：Equivalent Fault Collapsing 课时19：Dominance Fault Collapsing, DFC (_optional) 课时20：FaultSim Intro 课时21：FaultSim Parallel 课时22：FaultSim Deductive 课时23：Concurrent Fault Simulation 课时24：FaultSim DiffFsim 课时25：FaultSim Alternatives 课时26：FaultSim IssueConclusion (_optional) 课时27：Testability Intro 课时28：Testability SCOAPseq (_optional) 课时29：Testability COP 课时30：Combinational ATPG Introduction 课时31：Combinational ATPG (Boolean Difference) 课时32：Combinational ATPG (Single Path Sensitization) 课时33：Combinational ATPG, D_algorithm 课时34：Combinational ATPG, PODEM 课时35：Combinational ATPG, FAN 课时36：Combinational ATPG, SAT 课时37：Combinational ATPG, acceleration techniques 课时38：Sequential ATPG Introduction 课时39：Sequential ATPG (9_valued) 课时40：Sequential ATPG (Backward Time Frame Processing) 课时41：Sequential ATPG Simulation (_optional) 课时42：Sequential ATPG Conclusion (_optional) 课时43：DelayTest Intro 课时44：Delay Test _ Path Sensitize 课时45：DelayTest PathTG 课时46：DelayTest PathFsim 课时47：DelayTest TransitionFsimTG 课时48：Diagnosis Intro 课时49：Diagnosis StaticCE 课时50：Diagnosis DynamicCE 课时51：Diagnosis EffectCause 课时52：Diagnosis, Chain Diagnosis (_optional) 课时53：DFT1 Intro 课时54：DFT1 ScanConcepts 课时55：DFT1 _ Test Mode Operation (SSF & Delay Test LOS_LOC) 课时56：DFT1 Muxed_D Scan ATPG model (_optional) 课时57：DFT1 ClockScan (_optional) 课时58：DFT1 LSSD 课时59：DFT1 ScanDesignFlow 课时60：DFT1 IssueSol 课时61：DFT2 JTAG Intro 课时62：DFT2 JTAG Registers 课时63：DFT2 JTAG Instruction 课时64：DFT2 JTAG Instruction (old version) 课时65：DFT2 Instruction2Conclude 课时66：BIST1 Intro 课时67：BIST1 LFSR 课时68：BIST1 _ LFSR seed solving 课时69：BIST1 LFSRpolynomial 课时70：BIST1 CA 课时71：BIST2 Intro 课时72：BIST2 SerialORA 课时73：BIST2 Parallel ORA MISR 课时74：BIST2 Architecture 课时75：BIST2 Design Phase Shifter for LFSR TPG 课时76：BIST2 IssuesConclude (_optional)_2 课时77：TestCompress Intro 课时78：TestCompress SoftwareSTC 课时79：Test Compress Hardware Stimulus (updated 5_10_2020) 课时80：TestCompress HardwareResponse (_optional) 课时81：MemTest Intro 课时82：Memory Test _ Classical algorithm 课时83：MemTest March 课时84：FunctionTest Intro 课时85：FunctionTest CheckExp 课时86：FunctionTest IOV 课时87：FunctionTest SV (_optional)