S3C2440 2440init.s分析第一篇（二）

;//2.根据工作频率设置pll

;这里介绍一下计算公式

;//Fpllo=(m*Fin)/(p*2^s)

;//m=MDIV+8,p=PDIV+2,s=SDIV

;The proper range of P and M: 1<=P<=62, 1<=M<=248

 

;Fpllo必须大于20Mhz小于66Mhz

;Fpllo*2^s必须小于170Mhz

;如下面的PLLCON设定中的M_DIV P_DIV S_DIV是取自option.h中

;#elif (MCLK==40000000)

;#define PLL_M (0x48)

;#define PLL_P (0x3)

;#define PLL_S (0x2)

;所以m=MDIV+8=80,p=PDIV+2=5,s=SDIV=2

;硬件使用晶振为10Mhz,即Fin=10Mhz

;Fpllo=80*10/5*2^2=40Mhz

 

    ;To reduce PLL lock time, adjust the LOCKTIME register.

    ldr    r0,=LOCKTIME

    ldr    r1,=0xffffff

    str    r1,[r0]

;//设置PLL的重置延迟

 

    [ PLL_ON_START

    ; Added for confirm clock divide. for 2440.

    ; Setting value Fclk:Hclk:Pclk

    ldr    r0,=CLKDIVN

    ldr    r1,=CLKDIV_VAL        ; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6.

    str    r1,][r0]                ;//数据表示分频数

 

    ;//Configure UPLL Fin=12.0MHz UFout=48MHz

    ldr    r0,=UPLLCON

    ldr    r1,=((U_MDIV<<12)+(U_PDIV<<4)+U_SDIV) ;//USB PLL CONFIG

    str    r1,[r0]

   

    nop    ;// Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.

    nop

    nop

    nop

    nop

    nop

    nop

    ;//Configure MPLL Fin=12.0MHz MFout=304.8MHz

    ldr    r0,=MPLLCON

    ldr    r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV)

    str    r1,[r0]

    ]

   

;//Check if the boot is caused by the wake-up from SLEEP mode.

    ldr    r1,=GSTATUS2

    ldr    r0,[r1]

    tst    r0,#0x2        ;test if bit[1] is 1 or 0 0->C=1

                    ;                          1->C=0

    ;In case of the wake-up from SLEEP mode, go to SLEEP_WAKEUP handler.

    bne    WAKEUP_SLEEP    ;C=0,jump

 

    EXPORT StartPointAfterSleepWakeUp

StartPointAfterSleepWakeUp

 

;//3.置存储相关寄存器的程序

;这是设置SDRAM,flash ROM 存储器连接和工作时序的程序,片选定义的程序

;SMRDATA map在下面的程序中定义

;SMRDATA中涉及的值请参考memcfg.s程序

;具体寄存器各位含义请参考s3c44b0 spec   

    ;Set memory control registers

     ldr    r0,=SMRDATA

    ldr    r1,=BWSCON    ;BWSCON Address

    add    r2, r0, #52    ;End address of SMRDATA

 

   

0

    ldr    r3, [r0], #4

    str    r3, [r1], #4

    cmp    r2, r0

    bne    %B0

;//set memory registers

 

 

;//4.初始化各模式下的栈指针

         ;Initialize stacks

    bl    InitStacks

   

   

 

;//5.设置缺省中断处理函数

      ; Setup IRQ handler

    ldr    r0,=HandleIRQ       ;This routine is needed

    ldr    r1,=IsrIRQ      ;if there isn't 'subs pc,lr,#4' at 0x18, 0x1c

    str    r1,[r0]

    ;//initialize the IRQ 将普通中断判断程序的入口地址给HandleIRQ

   

   

 

;//6.将数据段拷贝到ram中 将零初始化数据段清零 跳入C语言的main函数执行到这步结束bootloader初步引导结束

    ;If main() is used, the variable initialization will be done in __main().

   

    [    :LNOT:USE_MAIN    ;initialized {FALSE}

                          ;Copy and paste RW data/zero initialized data

                         

    LDR     r0, =|Image$$RO$$Limit| ; Get pointer to ROM data

    LDR     r1, =|Image$$RW$$Base| ; and RAM copy

    LDR     r3, =|Image$$ZI$$Base|

   

    ;Zero init base => top of initialised data

    CMP     r0, r1      ; Check that they are different just for debug??????????????????????????

    BEQ     %F2

1      

    CMP     r1, r3      ; Copy init data

    LDRCC   r2, ][r0], #4    ;--> LDRCC r2, [r0] + ADD r0, r0, #4        

    STRCC   r2, [r1], #4    ;--> STRCC r2, [r1] + ADD r1, r1, #4

    BCC     %B1

2      

    LDR     r1, =|Image$$ZI$$Limit| ; Top of zero init segment

    MOV     r2, #0

3      

    CMP     r3, r1      ; Zero init

    STRCC   r2, [r3], #4

    BCC     %B3

    ]

 

 

      

    [ :LNOT:THUMBCODE    ;if thumbcode={false} bl main

        bl    Main        ;Don't use main() because ......

        b    .                      

    ]

 

 

;//if thumbcod={ture}

    [ THUMBCODE         ;for start-up code for Thumb mode

        orr    lr,pc,#1

        bx    lr

        CODE16

        bl    Main        ;Don't use main() because ......

        b    .

        CODE32

    ]

 

 

;function initializing stacks

InitStacks

    ;Don't use DRAM,such as stmfd,ldmfd......

    ;SVCstack is initialized before

    ;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'

   

    mrs    r0,cpsr

    bic    r0,r0,#MODEMASK

    orr    r1,r0,#UNDEFMODE|NOINT

    msr    cpsr_cxsf,r1        ;UndefMode

    ldr    sp,=UndefStack        ; UndefStack=0x33FF_5C00

 

    orr    r1,r0,#ABORTMODE|NOINT

    msr    cpsr_cxsf,r1        ;AbortMode

    ldr    sp,=AbortStack        ; AbortStack=0x33FF_6000

 

    orr    r1,r0,#IRQMODE|NOINT

    msr    cpsr_cxsf,r1        ;IRQMode

    ldr    sp,=IRQStack        ; IRQStack=0x33FF_7000

 

    orr    r1,r0,#FIQMODE|NOINT

    msr    cpsr_cxsf,r1        ;FIQMode

    ldr    sp,=FIQStack        ; FIQStack=0x33FF_8000

 

    bic    r0,r0,#MODEMASK|NOINT

    orr    r1,r0,#SVCMODE

    msr    cpsr_cxsf,r1        ;SVCMode

    ldr    sp,=SVCStack        ; SVCStack=0x33FF_5800

 

    ;USER mode has not be initialized.

    ;//为什么不用初始化user的stacks，系统刚启动的时候运行在哪个模式下？？？？？？？？？？？？？？？？？？？

    mov    pc,lr

    ;The LR register won't be valid if the current mode is not SVC mode.？？？？？？？？？？？？？

;//系统一开始运行就是SVCmode？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？

   

;=====================================================================

; Clock division test

; Assemble code, because VSYNC time is very short

;=====================================================================

    EXPORT CLKDIV124

    EXPORT CLKDIV144

   

CLKDIV124

   

    ldr     r0, = CLKDIVN

    ldr     r1, = 0x3        ; 0x3 = 1:2:4

    str     r1, [r0]

;    wait until clock is stable

    nop

    nop

    nop

    nop

    nop

 

    ldr     r0, = REFRESH

    ldr     r1, [r0]

    bic        r1, r1, #0xff

    bic        r1, r1, #(0x7<<8)

    orr        r1, r1, #0x470    ; REFCNT135

    str     r1, [r0]

    nop

    nop

    nop

    nop

    nop

    mov     pc, lr

 

CLKDIV144

    ldr     r0, = CLKDIVN

    ldr     r1, = 0x4        ; 0x4 = 1:4:4

    str     r1, [r0]

;    wait until clock is stable

    nop

    nop

    nop

    nop

    nop

 

    ldr     r0, = REFRESH

    ldr     r1, [r0]

    bic        r1, r1, #0xff

    bic        r1, r1, #(0x7<<8)

    orr        r1, r1, #0x630    ; REFCNT675 - 1520

    str     r1, [r0]

    nop

    nop

    nop

    nop

    nop

    mov     pc, lr

 

 

;存储器控制寄存器的定义区

    LTORG

 

SMRDATA DATA

; Memory configuration should be optimized for best performance

; The following parameter is not optimized.

; Memory access cycle parameter strategy

; 1) The memory settings is safe parameters even at HCLK=75Mhz.

; 2) SDRAM refresh period is for HCLK<=75Mhz.

 

    DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))

    DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))   ;GCS0

    DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))   ;GCS1

    DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))   ;GCS2

    DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))   ;GCS3

    DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))   ;GCS4

    DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))   ;GCS5

    DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))    ;GCS6

    DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))    ;GCS7

    DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)

 

    DCD 0x32        ;SCLK power saving mode, BANKSIZE 128M/128M

 

    DCD 0x30        ;MRSR6 CL=3clk

    DCD 0x30        ;MRSR7 CL=3clk

 

 

    ALIGN

 

    AREA RamData, DATA, READWRITE

 

    ^   _ISR_STARTADDRESS        ; _ISR_STARTADDRESS=0x33FF_FF00

HandleReset     #   4

HandleUndef     #   4

HandleSWI        #   4

HandlePabort    #   4

HandleDabort    #   4

HandleReserved #   4

HandleIRQ        #   4

HandleFIQ        #   4

 

;Don't use the label 'IntVectorTable',

;The value of IntVectorTable is different with the address you think it may be.

;IntVectorTable

;@0x33FF_FF20

HandleEINT0        #   4

HandleEINT1        #   4

HandleEINT2        #   4

HandleEINT3        #   4

HandleEINT4_7    #   4

HandleEINT8_23    #   4

HandleCAM        #   4        ; Added for 2440.

HandleBATFLT    #   4

HandleTICK        #   4

HandleWDT        #   4

HandleTIMER0     #   4

HandleTIMER1     #   4

HandleTIMER2     #   4

HandleTIMER3     #   4

HandleTIMER4     #   4

HandleUART2      #   4

;@0x33FF_FF60

HandleLCD         #   4

HandleDMA0        #   4

HandleDMA1        #   4

HandleDMA2        #   4

HandleDMA3        #   4

HandleMMC        #   4

HandleSPI0        #   4

HandleUART1        #   4

HandleNFCON        #   4        ; Added for 2440.

HandleUSBD        #   4

HandleUSBH        #   4

HandleIIC        #   4

HandleUART0     #   4

HandleSPI1         #   4

HandleRTC         #   4

HandleADC         #   4

;@0x33FF_FFA0

    END