S3C2440 2440init.s分析第二篇（二）

;*****************************************************************************
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;终说见到艳阳天了!!!!!!!!!!
;       跳到C语言的main函数处了.
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;*****************************************************************************
    [ :LNOT:THUMBCODE
   bl Main ;Do not use main() because ......
   ;ldr pc, =Main ;hzh
   b .
    ]

    [ THUMBCODE ;for start-up code for Thumb mode
   orr lr,pc,#1
   bx lr
   CODE16
   bl Main ;Do not use main() because ......
   b .
CODE32
    ]


;function initializing stacks
InitStacks
;Do not use DRAM,such as stmfd,ldmfd......
;SVCstack is initialized before
;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr_cxsf,r1 ;UndefMode
ldr sp,=UndefStack ; UndefStack=0x33FF_5C00

orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 ;AbortMode
ldr sp,=AbortStack ; AbortStack=0x33FF_6000

orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 ;IRQMode
ldr sp,=IRQStack ; IRQStack=0x33FF_7000

orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 ;FIQMode
ldr sp,=FIQStack ; FIQStack=0x33FF_8000

bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 ;SVCMode
ldr sp,=SVCStack ; SVCStack=0x33FF_5800

;USER mode has not be initialized.

mov pc,lr
;The LR register will not be valid if the current mode is not SVC mode.

;===========================================================
ReadNandID
mov      r7,#NFCONF
ldr      r0,[r7,#4] ;NFChipEn();
bic      r0,r0,#2
str      r0,[r7,#4]
mov      r0,#0x90 ;WrNFCmd(RdIDCMD);
strb     r0,[r7,#8]
mov      r4,#0   ;WrNFAddr(0);
strb     r4,[r7,#0xc]
1       ;while(NFIsBusy());
ldr      r0,[r7,#0x20]
tst      r0,#1
beq      %B1
ldrb     r0,[r7,#0x10] ;id = RdNFDat()<<8;
mov      r0,r0,lsl #8
ldrb     r1,[r7,#0x10] ;id |= RdNFDat();
orr      r5,r1,r0
ldr      r0,[r7,#4] ;NFChipDs();
orr      r0,r0,#2
str      r0,[r7,#4]
mov   pc,lr

ReadNandStatus
mov   r7,#NFCONF
ldr      r0,[r7,#4] ;NFChipEn();
bic      r0,r0,#2
str      r0,[r7,#4]
mov      r0,#0x70 ;WrNFCmd(QUERYCMD);
strb     r0,[r7,#8]
ldrb     r1,[r7,#0x10] ;r1 = RdNFDat();
ldr      r0,[r7,#4] ;NFChipDs();
orr      r0,r0,#2
str      r0,[r7,#4]
mov   pc,lr

WaitNandBusy
mov      r0,#0x70 ;WrNFCmd(QUERYCMD);
mov      r1,#NFCONF
strb     r0,[r1,#8]
1       ;while(!(RdNFDat()&0x40));
ldrb     r0,[r1,#0x10]
tst      r0,#0x40
beq   %B1
mov      r0,#0   ;WrNFCmd(READCMD0);
strb     r0,[r1,#8]
mov      pc,lr

CheckBadBlk
mov r7, lr
mov r5, #NFCONF

bic      r0,r0,#0x1f ;addr &= ~0x1f;
ldr      r1,[r5,#4] ;NFChipEn()
bic      r1,r1,#2
str      r1,[r5,#4]

mov      r1,#0x50 ;WrNFCmd(READCMD2)
strb     r1,[r5,#8]
mov      r1, #5;6 ;6->5
strb     r1,[r5,#0xc] ;WrNFAddr(5);(6) 6->5
strb     r0,[r5,#0xc] ;WrNFAddr(addr)
mov      r1,r0,lsr #8 ;WrNFAddr(addr>>8)
strb     r1,[r5,#0xc]
cmp      r6,#0   ;if(NandAddr)  
movne    r0,r0,lsr #16 ;WrNFAddr(addr>>16)
strneb   r0,[r5,#0xc]

; bl WaitNandBusy ;WaitNFBusy()
;do not use WaitNandBusy, after WaitNandBusy will read part A!
mov r0, #100
1
subs r0, r0, #1
bne %B1
2
ldr r0, [r5, #0x20]
tst r0, #1
beq %B2

ldrb r0, [r5,#0x10] ;RdNFDat()
sub r0, r0, #0xff

mov      r1,#0   ;WrNFCmd(READCMD0)
strb     r1,[r5,#8]

ldr      r1,[r5,#4] ;NFChipDs()
orr      r1,r1,#2
str      r1,[r5,#4]

mov pc, r7

ReadNandPage
mov   r7,lr
mov      r4,r1
mov      r5,#NFCONF

ldr      r1,[r5,#4] ;NFChipEn()
bic      r1,r1,#2
str      r1,[r5,#4]

mov      r1,#0   ;WrNFCmd(READCMD0)
strb     r1,[r5,#8]
strb     r1,[r5,#0xc] ;WrNFAddr(0)
strb     r0,[r5,#0xc] ;WrNFAddr(addr)
mov      r1,r0,lsr #8 ;WrNFAddr(addr>>8)
strb     r1,[r5,#0xc]
cmp      r6,#0   ;if(NandAddr)  
movne    r0,r0,lsr #16 ;WrNFAddr(addr>>16)
strneb   r0,[r5,#0xc]

ldr      r0,[r5,#4] ;InitEcc()
orr      r0,r0,#0x10
str      r0,[r5,#4]

bl       WaitNandBusy ;WaitNFBusy()

mov      r0,#0   ;for(i=0; i<512; i++)
1
ldrb     r1,[r5,#0x10] ;buf[i] = RdNFDat()
strb     r1,[r4,r0]
add      r0,r0,#1
bic      r0,r0,#0x10000
cmp      r0,#0x200
bcc      %B1

ldr      r0,[r5,#4] ;NFChipDs()
orr      r0,r0,#2
str      r0,[r5,#4]
  
mov   pc,r7

;--------------------LED test
EXPORT Led_Test
Led_Test
mov r0, #0x56000000
mov r1, #0x5500
str r1, [r0, #0x50]
0
mov r1, #0x50
str r1, [r0, #0x54]
mov r2, #0x100000
1
subs r2, r2, #1
bne %B1

mov r1, #0xa0
str r1, [r0, #0x54]
mov r2, #0x100000
2
subs r2, r2, #1
bne %B2
b %B0
mov pc, lr

;===========================================================

LTORG

;GCS0->SST39VF1601
;GCS1->16c550
;GCS2->IDE
;GCS3->CS8900
;GCS4->DM9000
;GCS5->CF Card
;GCS6->SDRAM
;GCS7->unused

SMRDATA DATA
; Memory configuration should be optimized for best performance
; The following parameter is not optimized.
; Memory access cycle parameter strategy
; 1) The memory settings is safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK<=75Mhz.

DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))   ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))   ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))   ;GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))   ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))   ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))   ;GCS5
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))    ;GCS6
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))    ;GCS7
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Tsrc<<18)+(Tchr<<16)+REFCNT)

DCD 0x32     ;SCLK power saving mode, BANKSIZE 128M/128M

DCD 0x30     ;MRSR6 CL=3clk
DCD 0x30     ;MRSR7 CL=3clk

BaseOfROM DCD |Image$$RO$$Base|
TopOfROM DCD |Image$$RO$$Limit|
BaseOfBSS DCD |Image$$RW$$Base|
BaseOfZero DCD |Image$$ZI$$Base|
EndOfBSS DCD |Image$$ZI$$Limit|

ALIGN

;Function for entering power down mode
; 1. SDRAM should be in self-refresh mode.
; 2. All interrupt should be maksked for SDRAM/DRAM self-refresh.
; 3. LCD controller should be disabled for SDRAM/DRAM self-refresh.
; 4. The I-cache may have to be turned on.
; 5. The location of the following code may have not to be changed.

;void EnterPWDN(int CLKCON);
EnterPWDN
mov r2,r0 ;r2=rCLKCON
tst r0,#0x8 ;SLEEP mode?
bne ENTER_SLEEP

ENTER_STOP
ldr r0,=REFRESH
ldr r3,[r0] ;r3=rREFRESH
mov r1, r3
orr r1, r1, #BIT_SELFREFRESH
str r1, [r0] ;Enable SDRAM self-refresh

mov r1,#16   ;wait until self-refresh is issued. may not be needed.
0 subs r1,r1,#1
bne %B0

ldr r0,=CLKCON ;enter STOP mode.
str r2,[r0]

mov r1,#32
0 subs r1,r1,#1 ;1) wait until the STOP mode is in effect.
bne %B0 ;2) Or wait here until the CPU&Peripherals will be turned-off
   ;   Entering SLEEP mode, only the reset by wake-up is available.

ldr r0,=REFRESH ;exit from SDRAM self refresh mode.
str r3,[r0]

MOV_PC_LR

ENTER_SLEEP
;NOTE.
;1) rGSTATUS3 should have the return address after wake-up from SLEEP mode.

ldr r0,=REFRESH
ldr r1,[r0] ;r1=rREFRESH
orr r1, r1, #BIT_SELFREFRESH
str r1, [r0] ;Enable SDRAM self-refresh

mov r1,#16   ;Wait until self-refresh is issued,which may not be needed.
0 subs r1,r1,#1
bne %B0

ldr r1,=MISCCR
ldr r0,[r1]
orr r0,r0,#(7<<17) ;Set SCLK0=0, SCLK1=0, SCKE=0.
str r0,[r1]

ldr r0,=CLKCON ; Enter sleep mode
str r2,[r0]

b .   ;CPU will die here.


WAKEUP_SLEEP
;Release SCLKn after wake-up from the SLEEP mode.
ldr r1,=MISCCR
ldr r0,[r1]
bic r0,r0,#(7<<17) ;SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:0->=SCKE.
str r0,[r1]

;Set memory control registers
ldr r0,=SMRDATA ;be careful!, hzh
ldr r1,=BWSCON ;BWSCON Address
add r2, r0, #52 ;End address of SMRDATA
0
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B0

mov r1,#256
0 subs r1,r1,#1 ;1) wait until the SelfRefresh is released.
bne %B0

ldr r1,=GSTATUS3 ;GSTATUS3 has the start address just after SLEEP wake-up
ldr r0,[r1]

mov pc,r0

;=====================================================================
; Clock division test
; Assemble code, because VSYNC time is very short
;=====================================================================
EXPORT CLKDIV124
EXPORT CLKDIV144

CLKDIV124

ldr     r0, = CLKDIVN
ldr     r1, = 0x3 ; 0x3 = 1:2:4
str     r1, [r0]
; wait until clock is stable
nop
nop
nop
nop
nop

ldr     r0, = REFRESH
ldr     r1, [r0]
bic r1, r1, #0xff
bic r1, r1, #(0x7<<8)
orr r1, r1, #0x470 ; REFCNT135
str     r1, [r0]
nop
nop
nop
nop
nop
mov     pc, lr

CLKDIV144
ldr     r0, = CLKDIVN
ldr     r1, = 0x4 ; 0x4 = 1:4:4
str     r1, [r0]
; wait until clock is stable
nop
nop
nop
nop
nop

ldr     r0, = REFRESH
ldr     r1, [r0]
bic r1, r1, #0xff
bic r1, r1, #(0x7<<8)
orr r1, r1, #0x630 ; REFCNT675 - 1520
str     r1, [r0]
nop
nop
nop
nop
nop
mov     pc, lr


ALIGN

AREA RamData, DATA, READWRITE

^   _ISR_STARTADDRESS ; _ISR_STARTADDRESS=0x33FF_FF00
HandleReset #   4
HandleUndef #   4
HandleSWI #   4
HandlePabort    #   4
HandleDabort    #   4
HandleReserved #   4
HandleIRQ #   4
HandleFIQ #   4

;Do not use the label 'IntVectorTable',
;The value of IntVectorTable is different with the address you think it may be.
;IntVectorTable
;@0x33FF_FF20
HandleEINT0 #   4
HandleEINT1 #   4
HandleEINT2 #   4
HandleEINT3 #   4
HandleEINT4_7 #   4
HandleEINT8_23 #   4
HandleCAM #   4 ; Added for 2440.
HandleBATFLT #   4
HandleTICK #   4
HandleWDT #   4
HandleTIMER0 #   4
HandleTIMER1 #   4
HandleTIMER2 #   4
HandleTIMER3 #   4
HandleTIMER4 #   4
HandleUART2   #   4
;@0x33FF_FF60
HandleLCD   #   4
HandleDMA0 #   4
HandleDMA1 #   4
HandleDMA2 #   4
HandleDMA3 #   4
HandleMMC #   4
HandleSPI0 #   4
HandleUART1 #   4
HandleNFCON #   4 ; Added for 2440.
HandleUSBD #   4
HandleUSBH #   4
HandleIIC #   4
HandleUART0 #   4
HandleSPI1   #   4
HandleRTC   #   4
HandleADC   #   4
;@0x33FF_FFA0
END