stm32F4各个库文件的作用分析

system_stm32f4xx.c：This file contains the system clock configuration for STM32F4xx devices.

  1 /**

  2   ******************************************************************************

  3   * @file    system_stm32f4xx.c

  4   * @author  MCD Application Team

  5   * @version V1.4.0

  6   * @date    04-August-2014

  7   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.

  8   *          This file contains the system clock configuration for STM32F4xx devices.

  9   *             

 10   * 1.  This file provides two functions and one global variable to be called from 

 11   *     user application:

 12   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier

 13   *                      and Divider factors, AHB/APBx prescalers and Flash settings),

 14   *                      depending on the configuration made in the clock xls tool. 

 15   *                      This function is called at startup just after reset and 

 16   *                      before branch to main program. This call is made inside

 17   *                      the "startup_stm32f4xx.s" file.

 18   *

 19   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used

 20   *                                  by the user application to setup the SysTick 

 21   *                                  timer or configure other parameters.

 22   *                                     

 23   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must

 24   *                                 be called whenever the core clock is changed

 25   *                                 during program execution.

 26   *

 27   * 2. After each device reset the HSI (16 MHz) is used as system clock source.

 28   *    Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to

 29   *    configure the system clock before to branch to main program.

 30   *

 31   * 3. If the system clock source selected by user fails to startup, the SystemInit()

 32   *    function will do nothing and HSI still used as system clock source. User can 

 33   *    add some code to deal with this issue inside the SetSysClock() function.

 34   *

 35   * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define

 36   *    in "stm32f4xx.h" file. When HSE is used as system clock source, directly or

 37   *    through PLL, and you are using different crystal you have to adapt the HSE

 38   *    value to your own configuration.

 39   *

 40   * 5. This file configures the system clock as follows:

 41   *=============================================================================

 42   *=============================================================================

 43   *                    Supported STM32F40xxx/41xxx devices

 44   *-----------------------------------------------------------------------------

 45   *        System Clock source                    | PLL (HSE)

 46   *-----------------------------------------------------------------------------

 47   *        SYSCLK(Hz)                             | 168000000

 48   *-----------------------------------------------------------------------------

 49   *        HCLK(Hz)                               | 168000000

 50   *-----------------------------------------------------------------------------

 51   *        AHB Prescaler                          | 1

 52   *-----------------------------------------------------------------------------

 53   *        APB1 Prescaler                         | 4

 54   *-----------------------------------------------------------------------------

 55   *        APB2 Prescaler                         | 2

 56   *-----------------------------------------------------------------------------

 57   *        HSE Frequency(Hz)                      | 25000000

 58   *-----------------------------------------------------------------------------

 59   *        PLL_M                                  | 25

 60   *-----------------------------------------------------------------------------

 61   *        PLL_N                                  | 336

 62   *-----------------------------------------------------------------------------

 63   *        PLL_P                                  | 2

 64   *-----------------------------------------------------------------------------

 65   *        PLL_Q                                  | 7

 66   *-----------------------------------------------------------------------------

 67   *        PLLI2S_N                               | NA

 68   *-----------------------------------------------------------------------------

 69   *        PLLI2S_R                               | NA

 70   *-----------------------------------------------------------------------------

 71   *        I2S input clock                        | NA

 72   *-----------------------------------------------------------------------------

 73   *        VDD(V)                                 | 3.3

 74   *-----------------------------------------------------------------------------

 75   *        Main regulator output voltage          | Scale1 mode

 76   *-----------------------------------------------------------------------------

 77   *        Flash Latency(WS)                      | 5

 78   *-----------------------------------------------------------------------------

 79   *        Prefetch Buffer                        | ON

 80   *-----------------------------------------------------------------------------

 81   *        Instruction cache                      | ON

 82   *-----------------------------------------------------------------------------

 83   *        Data cache                             | ON

 84   *-----------------------------------------------------------------------------

 85   *        Require 48MHz for USB OTG FS,          | Disabled

 86   *        SDIO and RNG clock                     |