08:30-09:00

Registration and morning light breakfast

09:00-09:05

Opening Ceremony

James Liu, GM & VP sales, Cadence Design Systems

09:05-09:25

Keynote: Opportunities, Challenges, and Collaboration

Lip-Bu Tan, President and CEO, Cadence Design Systems

09:25-09:50

Keynote presentation

Dr. Wei Shaojun, Director, Institute of Microelectronics, Tsinghua University

09:50-10:15

Keynote: Realizing Best Performance, Power, Area, and Yield for the 2x Nanometer Era

Chi-Ping Hsu, Senior VP R&D, Cadence Design Systems

10:15-10:30

Morning Break

(Demo booth & Exhibition open)

10:30-11:55

Panel discussion (Theme: Aggregate or Disaggregate? Chinese semiconductor industry trend in the next 10 years)

Moderator: Charlie Huang, Senior VP, Worldwide Field Operations, Cadence Design Systems;

6 key executive panelists from China IC Ecosystem

11:55-12:00

Best Paper Award Ceremony

12:00-13:00

Lunch

(Demo booth open during 12:30-13:00)

Digital

Custom/Analog

System Design & Functional Verification

IC Packaging and PCB Design

Design & Verification IP

13:00-13:30

D-01 Encounter RTL-to-Signoff technology overview and roadmap

--Cadence

C-01 Custom Design And Simulation (CAS) Technology Overview --Cadence

S-01 Functional Verification Overview

--Cadence

P-01 PCB and IC Packaging Technology Overview including Introduction of Sigrity Technology

--Cadence

I-01 Design & Verification IP technology overview

--Cadence

13:30-14:00

D-02 Cadence Silicon Signoff and Verification Solutions Update--Cadence

C-02 PVS: design and signoff with confidence--Cadence

S-02 Next generation SoC co-development with Cadence’s System Development Suite--Cadence

I-02 Reducing IC size, power and cost through early chip planning --Cadence

14:00-14:25

D-03 Customer Presentation

--ARM

C-03 Block and Chip level AMS Designer verification

--NationalZ

S-03 A comprehensive approach to scalable Framework for both vertical and horizontal reuse in UVM verification

--AMD

P-02 A new Methodology of Power Design and Analysis with Allegro PCB PDN

--Ericsson

I-03 customer presentation

--ZTE

14:25-14:50

D-04 The implementation of Smartphone chip including Cortex TM-A5 core at Cadence Platform

--Spreadtrum

C-04 Using RelXpert to do performance degradation and lifetime simulation on mos device

--Analogix

S-04 Best Practice of Wreal Based Analog Modeling

--LSI

P-03 Building a PCB design quality assurance system

—Huawei

I-04 Customer presentation

--Brite Semi