ARM - STM32 使用11.0592MHz晶振

这里探究了以下stm32 外部时钟的用法。

这里用的是stm32f103rbt6，usart2，外部晶振11.0592Mhz。

先看时钟树吧

这是上图的配置：

void RCC_Init(void)

{

ErrorStatus      HSEStartUpStatus;

RCC_DeInit();

RCC_HSEConfig(RCC_HSE_ON);   //设置外部高速晶振（HSE）

HSEStartUpStatus = RCC_WaitForHSEStartUp(); //等待HSE起振

if(HSEStartUpStatus == SUCCESS) //SUCCESS：HSE晶振稳定且就绪

{

RCC_HCLKConfig(RCC_SYSCLK_Div1);  //设置AHB时钟（HCLK）,RCC_SYSCLK_Div1——AHB时钟 = 系统时钟

RCC_PCLK2Config(RCC_HCLK_Div1); //设置高速AHB时钟（PCLK2）,RCC_HCLK_Div1——APB2时钟 = HCLK

RCC_PCLK1Config(RCC_HCLK_Div2); //设置低速AHB时钟（PCLK1）,RCC_HCLK_Div2——APB1时钟 = HCLK / 2

FLASH_SetLatency(FLASH_Latency_2);    //设置FLASH存储器延时时钟周期数,FLASH_Latency_2  2延时周期

FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); // 选择FLASH预取指缓存的模式,预取指缓存使能

RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_2);

// 设置PLL时钟源及倍频系数,PLL的输入时钟 = HSE时钟频率；RCC_PLLMul_2——PLL输入时钟x 2

RCC_PLLCmd(ENABLE);//使能PLL   

while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);//检查指定的RCC标志位(PLL准备好标志)设置与否   

RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); 

//设置系统时钟（SYSCLK）,RCC_SYSCLKSource_PLLCLK——选择PLL作为系统时钟,11.0592x2

while(RCC_GetSYSCLKSource() != 0x08);   //PLL返回用作系统时钟的时钟源,0x08：PLL作为系统时钟

  }

RCC_GetClocksFreq(&RCC_ClocksStatus);

}

这里的配置和上面的时钟树意义对应，下面读取时钟的函数可以得到各种时钟的值了。可以验证一下，你自己推算的对不对了。

  RCC_GetClocksFreq(&RCC_ClocksStatus);

  if (usartxbase == USART1_BASE)

  {

    apbclock = RCC_ClocksStatus.PCLK2_Frequency;

  }

  else

  {

    apbclock = RCC_ClocksStatus.PCLK1_Frequency;

  }

  /* Determine the integer part */

  if ((USARTx->CR1 & CR1_OVER8_Set) != 0)

  {

    /* Integer part computing in case Oversampling mode is 8 Samples */

    integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));    

  }

其中读取时钟的函数RCC_GetClocksFreq函数如下：

void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)

{

  uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;

#ifdef  STM32F10X_CL

  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;

#endif /* STM32F10X_CL */

#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)

  uint32_t prediv1factor = 0;

#endif

  /* Get SYSCLK source -------------------------------------------------------*/

  tmp = RCC->CFGR & CFGR_SWS_Mask;

  switch (tmp)

  {

    case 0x00:  /* HSI used as system clock */

      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;

      break;

    case 0x04:  /* HSE used as system clock */

      RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;

      break;

    case 0x08:  /* PLL used as system clock */

      /* Get PLL clock source and multiplication factor ----------------------*/

      pllmull = RCC->CFGR & CFGR_PLLMull_Mask;

      pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;

#ifndef STM32F10X_CL      

      pllmull = ( pllmull >> 18) + 2;

      if (pllsource == 0x00)

      {/* HSI oscillator clock divided by 2 selected as PLL clock entry */

        RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;

      }

      else

      {

 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)

       prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;

       /* HSE oscillator clock selected as PREDIV1 clock entry */

       RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; 

 #else

        /* HSE selected as PLL clock entry */

        if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)

        {/* HSE oscillator clock divided by 2 */

          RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;

        }

        else

        {

          RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;

        }

 #endif

      }

#else

      pllmull = pllmull >> 18;

      if (pllmull != 0x0D)

      {

         pllmull += 2;

      }

      else

      { /* PLL multiplication factor = PLL input clock * 6.5 */

        pllmull = 13 / 2; 

      }

      if (pllsource == 0x00)

      {/* HSI oscillator clock divided by 2 selected as PLL clock entry */

        RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;

      }

      else

      {/* PREDIV1 selected as PLL clock entry */

        /* Get PREDIV1 clock source and division factor */

        prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;

        prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;

        if (prediv1source == 0)

        { /* HSE oscillator clock selected as PREDIV1 clock entry */

          RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;          

        }

        else

        {/* PLL2 clock selected as PREDIV1 clock entry */

          /* Get PREDIV2 division factor and PLL2 multiplication factor */

          prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;

          pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; 

          RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         

        }

      }

#endif /* STM32F10X_CL */ 

      break;

    default:

      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;

      break;

  }

  /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/

  /* Get HCLK prescaler */

  tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;

  tmp = tmp >> 4;

  presc = APBAHBPrescTable[tmp];

  /* HCLK clock frequency */

  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;

  /* Get PCLK1 prescaler */

  tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;

  tmp = tmp >> 8;

  presc = APBAHBPrescTable[tmp];

  /* PCLK1 clock frequency */

  RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;

  /* Get PCLK2 prescaler */

  tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;

  tmp = tmp >> 11;

  presc = APBAHBPrescTable[tmp];

  /* PCLK2 clock frequency */

  RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;

  /* Get ADCCLK prescaler */

  tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;

  tmp = tmp >> 14;

  presc = ADCPrescTable[tmp];

  /* ADCCLK clock frequency */

  RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;

}

stm32f10x.h

#if !defined  HSE_VALUE

 #ifdef STM32F10X_CL   

  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */

 #else 

  #define HSE_VALUE    ((uint32_t)11059200) /*!< Value of the External oscillator in Hz */

 #endif /* STM32F10X_CL */

#endif /* HSE_VALUE */

void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)

{

  uint32_t tmpreg = 0x00, apbclock = 0x00;

  uint32_t integerdivider = 0x00;

  uint32_t fractionaldivider = 0x00;

  uint32_t usartxbase = 0;

  RCC_ClocksTypeDef RCC_ClocksStatus;

  /* Check the parameters */

  assert_param(IS_USART_ALL_PERIPH(USARTx));

  assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));  

  assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));

  assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));

  assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));

  assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));

  assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));

  /* The hardware flow control is available only for USART1, USART2 and USART3 */

  if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)

  {

    assert_param(IS_USART_123_PERIPH(USARTx));

  }

  usartxbase = (uint32_t)USARTx;

/*---------------------------- USART CR2 Configuration -----------------------*/

  tmpreg = USARTx->CR2;

  /* Clear STOP[13:12] bits */

  tmpreg &= CR2_STOP_CLEAR_Mask;

  /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/

  /* Set STOP[13:12] bits according to USART_StopBits value */

  tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;

  /* Write to USART CR2 */

  USARTx->CR2 = (uint16_t)tmpreg;

/*---------------------------- USART CR1 Configuration -----------------------*/