简介:好像时钟模块很复杂,其实,我们实际使用的时候比较简单,比如XT1外接一个32.768K晶振,XT2外接一个12M晶振,然后ACLK=XT1,MCLK=SMCLK=XT2,就好了,这里说的,主要是说说DCO,和内部自己震荡源,比较特殊,一般不怎么用,除非你没有任何外接晶振,只能使用内部的振荡器。
我给出一张截图,需要注意的我都标在上面了,图片需要放大观看的。
下面是TI提供的一个例程,我不多说,简单说几句。
//******************************************************************************
// MSP430F550x Demo - Software Toggle P1.1 with 12MHz DCO
//
// Description: Toggle P1.1 by xor'ing P1.1 inside of a software loop.
// ACLK is rought out on pin P1.0, SMCLK is brought out on P2.2, and MCLK
// is brought out on pin P4.7.
// ACLK = REFO = 32kHz, MCLK = SMCLK = 12MHz
//
// MSP430F550x
// -----------------
// /|| |
// | | P1.0|-->ACLK
// --|RST P4.7|-->MCLK
// | P2.2|-->SMCLK
// | |
// | P1.1|-->Port Pin
//
// D. Archbold
// Texas Instruments Inc.
// April 2009
// Built with CCSv4 and IAR Embedded Workbench Version: 4.21
//******************************************************************************
#include void SetVcoreUp (unsigned int level); void main(void) { volatile unsigned int i; WDTCTL = WDTPW+WDTHOLD;// Stop WDT PMAPPWD = 0x02D52;// Enable Write-access to modify port mapping registers P4MAP7 = PM_MCLK; PMAPPWD = 0;// Disable Write-Access to modify port mapping registers P1DIR |= BIT1; // P1.1 output P1DIR |= BIT0; // ACLK set out to pins P1SEL |= BIT0; P2DIR |= BIT2; // SMCLK set out to pins P2SEL |= BIT2; P4SEL |= BIT7; P4DIR |= BIT7; // MCLK set out to pins UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO UCSCTL4 |= SELA_2; // Set ACLK = REFO // Increase Vcore setting to level1 to support fsystem=12MHz // NOTE: Change core voltage one level at a time.. SetVcoreUp (0x01); // Initialize DCO to 12MHz __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_5; // Select DCO range 24MHz operation UCSCTL2 = FLLD_1 + 374; // Set DCO Multiplier for 12MHz // (N + 1) * FLLRef = Fdco // (374 + 1) * 32768 = 12MHz 对照图片上面的公式,应该很清楚了。因为FLLD_1就是上面的D,它是1,所以就给省略了。 // Set FLL Div = fDCOCLK/2 __bic_SR_register(SCG0); // Enable the FLL control loop // Worst-case settling time for the DCO when the DCO range bits have been // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx // UG for optimization. // 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle __delay_cycles(375000);这段话在MSP430F5510datasheet里面有说明的,自己可以找一下。 // Loop until XT1,XT2 & DCO fault flag is cleared do { UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags }while (SFRIFG1&OFIFG); // Test oscillator fault flag while(1) { P1OUT ^= BIT1; // Toggle P1.0 __delay_cycles(600000); // Delay } } void SetVcoreUp (unsigned int level) { // Open PMM registers for write PMMCTL0_H = PMMPW_H; // Set SVS/SVM high side new level SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level; // Set SVM low side to new level SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level; // Wait till SVM is settled while ((PMMIFG & SVSMLDLYIFG) == 0); // Clear already set flags PMMIFG &= ~(SVMLVLRIFG + SVMLIFG); // Set VCore to new level PMMCTL0_L = PMMCOREV0 * level; // Wait till new level reached if ((PMMIFG & SVMLIFG)) while ((PMMIFG & SVMLVLRIFG) == 0); // Set SVS/SVM low side to new level SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level; // Lock PMM registers for write access PMMCTL0_H = 0x00; }
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